1. Field of the Invention
The invention relates to a circuit arrangement for generating two signals staggered in time from a clock signal and for measuring their time stagger. The circuit arrangement comprises an input to which the clock signal is applied, a first output at which an undelayed signal generated from the clock signal is delivered, a second output at which a signal generated from the clock signal and delayed relative to the undelayed signal is delivered and a delay time measuring arrangement for measuring the time stagger between the delayed signal and the undelayed signal.
2. Description of the Prior Art
A prior art circuit arrangement of this kind comprises two inverters connected in series between the input of the circuit arrangement and the first output of the circuit arrangement. The delay time measuring arrangement comprises a NAND gate which receives at one input the delayed signal and at the other input the output signal of the first inverter which is the inverted clock signal. The NAND gate furnishes an output signal which depends on the time stagger existing between the two input signals of the NAND gate. The first inverter is needed because the output signal of the NAND gate represents the time stagger between two signals only when one of the two signals is inverted. The second inverter is needed for reconverting the inverted clock signal to its original form so that it can be used as an undelayed signal together with the delayed signal.
One problem particular to this prior art circuit arrangement resides in the fact that the time stagger determined from the output signal of the NAND gate does not correspond to the actual time stagger between the signals occuring at the two outputs of the circuit arrangement. The reason for this is that the undelayed signal appearing at the first output of the circuit arrangement is affected with the transit delay occuring in the second inverter needed for reconverting the signal, but this transit delay cannot be sensed by the NAND gate since the second inverter is located downstream of the circuit point at which the inverted clock signal is branched off to the NAND gate. This is the reason why there is an uncertainty as to the time stagger actually existing between the two signals appearing at the two outputs of the circuit arrangement, which uncertainty cannot be removed in the prior art circuit arrangement. This drawback is particularly serious when an extremely small and precisely defined time stagger needs to be achieved between the two signals.